Mobile communication standards with each new generation have enabled a new set of technologies that better the everyday human experience, and for those pioneers treading the unknown - opportunities. The physical layer (PHY) specifications of the fifth generation of mobile communications introduce variable timing constraints in the form of variable transmission time interval, depending on the subcarrier spacing configuration, along with the expansion of the throughput requirements. With the sixth generation expected to continue stretching the breadth of these requirements - even stricter timing constraints and use case dependant highly variable throughput, the significance of efficient PHY implementations is likely to become an opportunity for differentiation in the modem chip market. One way to handle the increased variability in PHY processing is with the application of the flexible digital signal processor (DSP) technology. In that light, the thesis sets its primary goal to analyse the applicability of DSPs in adapting the PHY system to operational circumstances and specific performance requirements. The flexibility of the DSP as a platform enables a high degree of freedom in mapping the PHY functionality and allows a trade-off between latency and efficiency in an implementation given some performance requirements like varied PHY timing constraints and throughput. Therefore, the secondary goal is to analyse the benefits of the latency-efficiency trade-off in PHY mapping on DSPs in respect to PHY specification requirements. To enable an investigation into these two goals the thesis proposes a framework for implementation of PHY signal processing algorithms for the next generation of specifications. To connect the implementation aspects and the specification requirements the framework places every implementation (hardware architecture, clock frequency, software implementation, signal processing algorithm, and workload size combination) on a two-dimensional rate-latency diagram, proposed to be called kernel timing response. The kernel timing response is used as a tool that captures changes between different implementations and use case requirements to help select the best-suited implementation for the given use case constraints. Although this method is developed to help analyse the applicability of DSPs, it can be easily adapted for analysis and optimisation of implementation on other machines with varied use case latency and throughput requirements. The proposed framework is then applied to investigate the application aspects of a very long instruction word (VLIW) single instruction, multiple data (SIMD) DSP in the implementation of multicarrier modulation filtering and channel estimation PHY processing steps, given the requirements at the intersection of the fifth and the sixth generation mobile communications. The analysis shows that the programmable vector processor platforms, like the VLIW SIMD DSP, are indeed well suited for the implementation of some of the key PHY processing steps under high-end requirements. The findings point to a to a high utilisation of parallel processing functional units under a limited clock frequency envelope and ability to mitigate the impact of varying timing constraints on the required frequency clock through low-cost mapping of algorithmic optimisations to specific use cases on software.weiterlesen