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Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design

A Self-test, Self-diagnosis, and Self-repair-based Approach

Produktform: Buch / Einband - fest (Hardcover)

With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield.   weiterlesen

Sprache(n): Englisch

ISBN: 978-9811985508 / 978-9811985508 / 9789811985508

Verlag: Springer Singapore

Erscheinungsdatum: 02.03.2023

Seiten: 304

Auflage: 1

Autor(en): Cheng Liu, Xiaowei Li, Guihai Yan

213,99 € inkl. MwSt.
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