The Josephson Arbitrary Waveform Synthesizer (JAWS) generates spectrally pure quantized AC voltages. It is also called pulse-driven AC Josephson voltage standard. To simplify the existing experimental set-up of the JAWS by reducing the number of RF cables at room temperature, to lower the cost of Pulse Pattern Generator and to increase the output voltage of JAWS in the future, on-chip RF power dividers were developed and continuously optimized. This thesis investigates the on-chip power dividers for JAWS focusing on the numerical simulation, its fabrication process, and measurement of the integrated circuits at 4K. In this work, there were three iteration steps in the circuit development. Firstly, two different types of RF power dividers were developed: the two-stage serial-parallel and the one-stage Wilkinson power divider. The outputs of the power dividers were integrated with bias-tee circuits and series arrays of non-stacked SNS type Josephson junctions (S: superconductor (Nb), N: normal metal (NbxSi1-x)). Both types of power dividers were successfully integrated into JAWS. With the Wilkinson power divider, output AC voltages of 18 mV (RMS) were obtained at a clock frequency of 15 GHz combined with a test array of 1,000 Josephson junctions. The test chip containing the serial-parallel power divider and a test array of 2,000 Josephson junctions generated RMS output voltages of 22 mV. In the second step, gained knowledge was used. And two new modified broadband Wilkinson power dividers were investigated: the one-stage three-section Wilkinson power divider has extended bandwidth compared to one-stage single-section Wilkinson divider; the two-stage single-section Wilkinson divider has no phase shift and good isolation between the outputs in contrast to the two-stage serial-parallel power divider. Both modified dividers were integrated with triple-stacked Josephson junction series arrays successfully. Spectrally pure sinusoidal waveforms were also successfully synthesized with both types of power dividers. With the one-stage three-section Wilkinson power divider combined with a test array of 3,000 Josephson junctions, a RMS voltage of nearly 53 mV was obtained at a clock frequency of 15 GHz. As for the two-stage single-section Wilkinson power divider combined with a test array of 6,000 Josephson junctions, RMS output voltages of about 105 mV was generated. To further increase the synthesized AC output voltage, the two-stage serial-parallel power divider and one-stage single-section Wilkinson divider were finally integrated with larger Josephson junction arrays (maximum 20,400 junctions per RF channel). The experimental results demonstrates a significant step forward. So far, a maximum RMS voltage of 600 mV per JAWS chip (300 mV per RF channel) has been realized. This represents a significant improvement over previous JAWS circuits and can be improved even further in the future.weiterlesen