explores the opportunity to reduce ADC power dissipation by leveraging digital signal processing capabilities in fine line integrated circuit technology. The described digitally assisted pipelined ADC uses a statistics-based system identification technique as an enabling element to replace precision residue amplifiers with simple open-loop gain stages. The digital compensation of analog circuit distortion eliminates one key factor in the classical noise-speed-linearity constraint loop and thereby enables a significant power reduction. describes in detail the implementation and measurement results of a 12-bit, 75-MSample/sec proof-of-concept prototype. The Experimental converter achieves power savings greater than 60% over conventional implementations. will be of interest to researchers and professionals interested in advances of state-of-the-art in A/D conversion techniques. weiterlesen