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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Produktform: E-Buch Text Elektronisches Buch in proprietärem

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.  weiterlesen

Dieser Artikel gehört zu den folgenden Serien

Elektronisches Format: PDF

Sprache(n): Englisch

ISBN: 978-9811010736 / 978-9811010736 / 9789811010736

Verlag: Springer Singapore

Erscheinungsdatum: 23.06.2017

Seiten: 197

Autor(en): Anupam Chattopadhyay, Zheng Wang

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