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High Level Synthesis of ASICs under Timing and Synchronization Constraints

Produktform: E-Buch Text Elektronisches Buch in proprietärem

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where design is of utmost importance. In contrast, ASIC designs are often characterized by complex schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: , and The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis. weiterlesen

Dieser Artikel gehört zu den folgenden Serien

Elektronisches Format: PDF

Sprache(n): Englisch

ISBN: 978-1-4757-2117-1 / 978-1475721171 / 9781475721171

Verlag: Springer US

Erscheinungsdatum: 14.03.2013

Seiten: 294

Autor(en): Giovanni DeMicheli, David C. Ku

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